As the design complexity of SoC grows, hardware/software (HW/SW) co-simulation becomes more and more crucial for early-stage system verification. To simplify the simulation efforts on register transfer level (RTL) designs, the concept of transaction-level modeling (TLM) for hardware was introduced. By adopting higher abstraction modeling, hardware simulation can be greatly accelerated while key operational information is maintained at the same time. Nevertheless, software is an essential system component, and it also requires proper abstraction models to be compatible with hardware TLM models for efficient HW/SW co-simulation. In particular, it is showed that the complexity of embedded software is rising 140 percent per year, which is greater than that of hardware at 56 percent per year. Obviously, abstraction for software is an urgent subject for investigation, and therefore some conventional approaches have developed in recent years.
Transaction-level modeling (TLM) is formally defined as a high-level approach to model digital systems where the communication among modules is separated from the functional units. A conventional approach integrates an ISS and SystemC. To enable the communication between the two different simulators, the conventional approach employed a bus functional model as a bridge. However, the ISS is quite slow (few MIPS only), and the expensive communication cost further downgrades the simulation speed. In general, the performance of ISS-SystemC co-simulation is unsatisfactory. Furthermore, the conventional approach compiles target source codes by the host compiler, such that target instructions are unavailable. It would make HW/SW interaction points unable to be accurately distinguished. Thus, the source-level software model is incapable of supporting HW/SW co-simulation comprehensively. Obviously, the aforementioned conventional approaches cannot meet the need of efficient and accurate timing synchronization in HW/SW co-simulation. Accordingly, there is still a need for a solution to solve the aforementioned problems in HW/SW co-simulation.